Microprocessor interrupt systems. The binary number system. Introduction to logical functions. Numerical and character codes. Semiconductor technologies. Semiconductor memories.
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The intel instruction set. The Motorola instruction set. Why do you need a personal computer? Z assembly language programming by Lance A Leventhal Book 8 editions published in in English and held by WorldCat member libraries worldwide. Lance Leventhal's programming guide by Lance A Leventhal Book 11 editions published between and in 4 languages and held by 90 WorldCat member libraries worldwide Beschrijving van de techniek en de mogelijkheden van deze bits microprocessor.
Assembly language subroutines for the by Lance A Leventhal Book 5 editions published in in English and held by 69 WorldCat member libraries worldwide. Assembly language subroutines for the by Lance A Leventhal Book 3 editions published in in English and held by 67 WorldCat member libraries worldwide. Audience Level. Related Identities. Also, it is typically more difficult for the microprocessor designer to implement the circuitry that incorporates various registers because it takes time to determine which register is to be used and to activate that register.
Streamlining internal operations so that this time is not detectable requires quite a bit of planning. So while fewer registers or dedicated registers may be easier for the microprocessor designer to implement, they make programming the new chip more cumbersome and less flexible. But the extra time, effort, and expense of implementing general-register principles pays off by easing the programming of these devices.
Design Philosophy Behind Motorola's MC68000
Therefore, the MC was designed with general-purpose registers. Any instruction may select any register for use as a source or destination operand or as a pointer in any allowable addressing mode. This tremendous flexibility gives programmers the ultimate in data and pointer placement.
A close observation of the use of registers indicates they usually have one of two purposes: they may retain data for manipulation, or they may contain an address that points to a memory location. The use of a register for each of these purposes is quite different. When data is moved into or out of a register or is manipulated within the register, all types of conditional information from the operation are important.
Thus, you typically would like all condition codes to be properly set after a data operation. This way these condition codes may be used to branch or with other data operations. On the other hand, an address might be placed in or taken from a register, or modified by incrementing or decrementing. Rarely is it important whether a carry comes out of the ALU or whether the result is negative i. In fact, a programmer would prefer manipulation of an address to have no effect on the condition codes.
Often in the middle of a complex data operation, you must bring in a new address or increment an address. To have this operation modify the condition codes most of the time will foul up the data operation in progress, and so is undesirable. Therefore, two generic register types emerge: a data register D0 through D7 and an address register A0 through A7. The MC has both types. In a data register, any operation will affect the condition codes of the microprocessor as is appropriate for the operation and the data used.
However, in an address-register operation, condition codes will not be changed, but the codes from previous data operations will be retained. This way you can have address and index pointer changes made, without affecting the accuracy of the results, in the middle of a complex data operation that requires many instructions and transfers from memory.
What size and how many of each type of register should be included in the microprocessor? The more registers there are, the better it is for the programmer. Unfortunately, the more register and control circuits in the chip, the more expensive it is. A good balance must be attained. Two registers are too few, four are nice, but it is difficult to imagine even a complex routine requiring more than eight different memory pointers.
The encoding of eight registers requires an even three bits. Because it seemed that eight was a good upper bound, the MC has eight address registers and also eight data registers. With 16 registers available, divided half and half for data and address, almost any sizable routine will never require the temporary storing of a value in a register just so that the register can be used for something else.
And, within the routine, manipulations of memory pointers in address registers will not interfere with an ongoing data calculation, because of the distinction of how the condition codes work for the different register types. It is easy to see how the MC is easier to program. Anyone who has ever programmed 8-bit microprocessors, which have 8-bit accumulators and bit index registers, has seen the difficulty with the two different sizes. Once programmers figure out how to put the bit value in both 8-bit accumulators, things get tougher when they try to get arithmetic carries from the lower half to the upper half of the value.
A little of this experience led the MC designers to decide that using data that is the same size as the address register could make some software design significantly easier. In order to handle a linear bit virtual-address space, the MC needed to have bit address registers. How would bit data registers fit into a bit microprocessor? You would expect a bit microprocessor to process 8- and bit data, but does it make sense for it to also process bit data?
Obviously, the addresses will have to be handled in that size. Designers recognized that in 8-bit microprocessors the ability to handle bit data came in quite handy for more advanced applications. The 8-bit processors soon had to be upgraded to handle bit operands, and users of bit mini-computers needed bit operations. Once a few bit operations become necessary in a microprocessor, you need a whole array of operations.
If a multiplication operation generates a bit result, in order to do anything with that result, other bit operations are needed.
For consistency, again, Motorola decided that the data registers would be 32 bits wide and operations on all 32 bits could take place with a single instruction. The exact manner of processing data and addresses through the MC came about later, with careful analysis of the internal architecture and the need for address and data in the sequence of instructions.
The chip ended up with three separate arithmetic units, which could work in parallel. I'll describe their purpose to give some insight into how the machine works. The MC has a bit-wide ALU that essentially performs all data calculations and provides single-pass evaluation of the bit data, for which the MC is primarily designed.
There are also two other internal arithmetic units. Both are 16 bits wide and are generally used in conjunction with each other to perform the various address calculations associated with operand effective addresses. This makes sense because all addresses are 32 bits wide.
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An effective address EA is the calculated result based on a selected addressing mode of the processor. In the MC, for instance, if an "index-register-plus-offset" address mode were used, the EA would be the result of adding the contents of X with the given offset. Because EA evaluation takes time and can be a significant portion of the instruction, it is important to perform this quickly. At one time, then, one bit address and one bit data calculation can take place within the MC This speeds instruction execution time considerably by processing addresses and data in parallel.
The MC also operates on bit data. This is usually done by taking two passes of bit data, one for the lower word and one for the upper word. This is reflected in the execution time of many and bit instructions. This prefetch queue is more intelligent than other microprocessor queues; its control varies according to the instruction stream contents.
The prefetch queue is a very effective means of increasing microprocessor performance; it attempts to have as much instruction information as possible available before a particular instruction begins execution. The microprocessor uses an otherwise idle data bus to prefetch from the instruction stream.
This keeps the bus active more of the time, increasing performance because processing of instructions is often limited by the time it takes to get all the relevant information into the processor. The part of memory from which instructions are fetched, the program space, contains op codes and addressing information.
The prefetch queue can contain enough information to execute one instruction, decode the next instruction, and fetch the following instruction from memory -- all at the same time. Exactly what is in the queue is very dependent upon the exact instruction sequences. The queue is intelligent enough to stay fairly full without being too wasteful. For instance, when a conditional branching instruction is detected, the prefetch is ready to either branch or not by the time a decision is made.
The queue tries to fetch both the op code following the branch instruction and the op code at the calculated branch location. Then, when the condition codes are compared and a decision is made whether to branch, the processor can begin immediate decoding of either instruction. The other unnecessary op code is ignored.
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You can use the prefetch queue in many other special ways as well. One example is in speeding up the repetitious Move Multiple Registers instruction, where it is used to accelerate successive data transfers. The prefetch queue allows many frequently used instructions to execute in exactly the time it takes to fetch the op code actually, the time to prefetch the next op code. One other significant implementation feature from the MACSS project emerged from the choice between a random logic design versus a microcoded design. Both techniques have advantages and disadvantages.
Earlier microprocessors were largely of random logic design. Advanced techniques of very large scale integration VLSI and the increasing complexity of the chips have made microcoding more attractive. Random logic design of a microprocessor or other logic device is the building of the device from discrete components-gates, buffers, and transistors.
Before the flood: The 1960s
This limits the components to those that are essential. There are no unused gates, duplicated circuits, or clever uses of otherwise unused components. The design is usually packed as tightly as possible and is quite fast. The difficulty is that, as the design becomes more and more complex, as VLSI has, the planning and layout of the components and signal traces become exponentially more difficult and often impossibly so. This means that it takes exorbitant amounts of time to design the circuits. Another problem with the use of random logic in very complex circuits occurs in modeling and testing.
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Before such circuits are finally placed in silicon, they must be modeled and simulated on computers because of the great difficulty in running down bugs once the chip is in silicon compared to debugging a wire-wrap board. The entire circuit must be modeled all at once to ensure that one combination of signals affects only the expected section of the device. You typically have only a few lines to send sequences of patterns through for testing.
Because a particular section of the circuit may be exercised only by a very few given inputs, a normal test may not detect a stuck gate or other error caused by some strange combination of inputs. Microprogramming is to a microprocessor what a microprocessor is to a logic design of a system. A microprocessor has central components that can be considered black boxes with inputs and outputs.
For each given operation instruction, interrupt condition, etc. The control of this routing is performed by a microcontroller or microsequencer. Similar to a microprocessor, the microsequencer directs the flow of data through the various components ALU, registers, condition flags, shifters, buses, etc. Each instruction has its own microroutine, or sequence of microwords, which routes the associated data to the proper component in the proper order.
Conditions and branches may redirect the microroutines. Microcoding a complex circuit simplifies design mostly because it makes the circuit modular. It takes a controller, a block of microprogram, and the components through which data is to flow.
Each of these elements may be modeled, built, and tested with individual inputs and outputs. Microcoding is a big step toward simplifying the design process because it breaks up the design into manageable blocks, thereby easing the testing of the finished product. Another advantage of microcoding is that it allows tremendous flexibility in the exact operation of the circuit.
Its microwords allow more combinations of the inputs through the components than most random logic would allow. Microcoding's programmability makes it especially attractive to silicon designers because random logic in silicon is not easily changed. You can change the microROM of the microcoded device right up to the minute before the masks for the device are processed. To change a small facet of an operation may mean altering a few bits in the microROM, but this changes only whether or not there is a gate on the bit's transistor-a simple alteration.
Similarly, after the silicon is cast, should a change be necessary, it will likely be just a microcode change, which would be much easier than random logic modification in silicon. The disadvantage of a microcoded circuit lies primarily in its generality. Because it is made up of modules and is programmed, the microcoded circuit is more wasteful of transistors and therefore makes a larger circuit.
This may add up to 20 percent more board space or chip area than a tight random logic design. But microcoding has advantages that make up for this disadvantage, making it the design choice for modern VLSI circuits. There are two types of microprogramming, horizontal and vertical see figure 4. Horizontal microcoding is the more direct form. It is unencoded, so that, for instance, 1 bit in each microword would enable each register. For 16 registers, then, 16 bits of microcode must be dedicated. Horizontal microwords tend to be quite long, and because the size of the microcode directly affects chip size, they can quickly increase chip cost.
A denser but slower form of microcoding is vertical microcoding. Here, control functions are encoded, so that only 4 bits of microcode are required to select one of 16 registers. While it needs a much shorter microword, vertical microprogramming is potentially slower than horizontal microprogramming. Vertical microprogramming will take at least one level of logic gates to decode the encoded signals.
This level of gates may just throw the total gate propagation delay over the threshold of the clock pickets, forcing an additional clock cycle into the instruction. In retrospect this was a very wise decision. The first silicon prototype worked well enough so that the major circuits in the device could be tested, and subsequent "fixes" were often just microcode corrections. The instruction set was not firm until just before the masks went to wafer fabrication, allowing some late decisions to be made to improve the performance of the chip.
A combination of horizontal and vertical microcoding was used on the MC to gain the optimum advantages of both. Essentially, a microcode and a nanocode were developed. The microcode is a series of pointers into assorted microsubroutines in the nanocode. The nanocode performs the actual routing and selecting of registers and functions, and directs results. This combination is quite efficient because a great deal of code can share many common routines and yet retain the individuality required of different instructions.
Decoding of an instruction's op code generates starting addresses in the microcode for the type of operation and the addressing mode. Completion of an instruction enables interrupts to be accepted or allows access to the prefetch queue for the next op code. The prefetch queue actually keeps bus use at 85 to 95 percent, i.
Let's look back now at the MC and see what parts of it might qualify it as a bit device. The internal data ALU is 16 bits. It processes bit addresses, though only 24 bits are brought off chip. The op code that tells the processor what operation to perform is 16 bits wide. The data bus is 16 bits wide. The microprocessor will operate on either 8, 16, or 32 bits of data automatically. There are 16 general-purpose bit-wide registers in the chip. The MC is generally considered a bit microprocessor, though it uses bit addresses and contains bit registers.
It also can operate on 32 bits of data as easily as 8 and Many users of the MC consider it a bit just as much as a bit processor. Whatever you consider it there is no doubt that the MC is indeed a powerful microprocessor. In coming articles, I will discuss in more detail exactly what operations are available in the MC and will illustrate examples of MC code. Motorola has recently developed an improved version of the MC the MC It is completely compatible with object codes of earlier versions of the and has added virtual memory support and improved loop instruction execution.
By using virtual memory techniques. The physical memory can be accessed by the micro processor while a much larger "virtual" memory is maintained as an image on a secondary storage device such as a floppy disk. When the microprocessor is instructed to access a location in the virtual memory that is not within the physical memory referred to as a page fault , the access is suspended while the location and data are retrieved from the floppy disk and placed into physical memory.
Then the suspended access is completed. The provides hardware support for virtual memory with the ability to suspend an instruction when a page fault is detected and then to complete the instruction after physical memory has been updated. The MC uses instruction continuation rather than instruction restart to support virtual memory.
When a page fault occurs, the microprocessor stores its internal state on the supervisor stack. When the page fault has been repaired, the previous internal state is reloaded into the microprocessor, and it continues with the suspended instruction. As mentioned in the body of this article, the uses a prefetch queue to improve the speed of instruction execution.